A CCD for transferring the charges in one direction under pulsed gate is widely used in various memory devices, logic circuits and signal processing, and the image pickup device.
The CCD stores the charges in the potential well created in the bulk of a semiconductor substrate and transports the stored charges in one direction according to the clock pulse applied to a gate.
FIG. 1 shows a sectional view of a conventional charge coupled device.
Referring to FIG. 1, a p type semiconductor substrate 11 is provided with an n type impurity area 12 including a multiplicity of lightly-doped n- type barrier areas 13 separated from each other by a constant distance.
A gate oxidation layer 14 is formed over the semiconductor substrate 11, and a plurality of first and second gate electrodes 15 and 16 are formed on each portion of the gate oxidation layer which corresponds to the -type impurity area 12 and the lightly-doped n- type barrier areas 13, respectively.
A plurality of lightly-doped n- type barrier areas 13 are formed in the n type impurity area 12 separated from each other by a constant distance, so that a consecutive H-L (High-Low) junction is made between a multiplicity of lightly-doped n-type barrier areas 13 and the n type impurity area 12.
The impurity concentration difference between n type impurity area 12 and n- type barrier area 13 makes it be formed a potential well as shown in FIG. 1B, even under the conditions that no voltage is applied to the first and second gates 15 and 16.
A plurality of first and second gate electrodes 25 and 26 each having a constant width are sequentially arrayed in the alternate form over the semiconductor substrate 21 and receive the clock pulses .phi.11, .phi.12. A plurality of first and second gate electrodes 15, 16 are generally made of such as polysilicon material. The first clock signal .phi.11 is applied to the adjacent odd second gate electrodes and even first gate electrodes 16-1 and 15-2, 16-3 and 15-4, . . . ,16-n-1 and 15-n through a signal line L11 connecting said gate electrodes together, and the second clock signal .phi.12 is applied to the adjacent even second gate electrodes and odd first gate electrodes 16-2 and 15-3, 16-4 and 15-5, . . . ,16-n and 15-n+1 through a signal line L12 connecting said gate electrodes together.
When the clock pulses .phi.11, .phi.12 of two-phase, which is shown in FIG. 3, are applied to a plurality of first and second gate electrodes 15, 16 of such a conventional CCD, the first clock signal .phi.11 is applied to the adjacent odd second gate electrodes and even first gate electrodes 16-1 and 15-2, 16-3 and 15-4, . . . ,16-n-1 and 15-n among a plurality of first and second gate electrodes 15, 16 through a signal line L11, and the second clock signal .phi.12 is applied to the adjacent even second gate electrodes and odd first gate electrodes 16-2 and 15-3, 16-4 and 15-5, . . . ,16-n and 15-n+1 through a signal line L12 among a plurality of first and second gate electrodes 15, 16. That is, in the case that the clock pulses .phi.11, .phi.12 of two-phase are applied as shown in FIG. 2, a signal of low level is provided through the first signal line L11 which is substantially .phi.11 clock signal line and a signal of high level provided through the second signal line L12 which is substantially .phi.12 clock signal line.
Accordingly, the low signal is applied to the adjacent odd second gate electrodes and even first gate electrodes 16-1 and 15-2, 16-3 and 15-4, . . . ,16-n-1 and 15-n among a plurality of first and second gate electrodes 15, 16, and the signal of high level is applied to the adjacent even second gate electrodes and odd first gate electrodes 16-2 and 15-3, 16-4 and 15-5, . . . ,16-n and 15-n+1, thereby it is obtained the potential distribution in the stepped form as shown in FIG. 3B.
Therefore a deep potential well in which the charges are stored appears in n-type impurity area 12 beneath odd first gate electrodes 15-1, 15-3, . . . ,15-n+1 according to said clock pulses .phi.11, .phi.12.
If, at a time point t=1, the clock pulses .phi.11, .phi.12 of two-phase are applied after a lapse of a time interval, the first and second clock signals as high and low level, in contradiction to the situation at a time point t=0 of FIG. 4A, are input into the first and second clock signal line L11 and L12, respectively.
Accordingly, the signal of high level is applied to the adjacent odd second gate electrodes and even first gate electrodes 16-1 and 15-2, 16-3 and 15-4, . . . ,16-n-1 and 15-n among a plurality of first and second gate electrodes 15, 16, and the signal of low level is applied to the adjacent even second gate electrodes and odd first gate electrodes 16-2 and 15-3, 16-4 and 15-5, . . . ,16-n and 15-n-1, thereby it is obtained a potential distribution in the stepped form as shown in FIG. 4B.
Therefore, the deep potential well appears in n type impurity area 12.
Thus, the stored charges in n type impurity area 12 beneath odd first gate electrodes 15-1,15-3, . . . ,15-n+1 at a time t=0 can be transferred and then stored in n type impurity area 12 beneath next even first gate electrodes 15-1,15-3, . . . ,15-n at a time t=1.
When the consecutive two-phase clock pulses .phi.11, .phi.12 are provided with the first and second gate electrodes 15,16, the charges are transferred from the left to the right, which the transferred signal is sensed by means of a sensing amplifier (not shown) and then is detected as the electrical signals of time-series.
It is necessary to convert directionality of the signal flow into the other direction so as to obtain a mirror image, but to accomplish that object, the conventional CCD requires additional shift register or memory means by which the data are written in FIFO (First-In Last Out) manner and then read-out, thereby the charge transfer flow being converted into the opposite direction.